1. Field of the Invention
This invention relates generally to data processing systems and more specifically to a processor within a data processing system.
2. Description of the Prior Art
The performance characteristics of any data processing system, such as that described in the U.S. Pat. Nos. 3,614,740, 3,614,741 and 3,710,324, all of which are assigned to the assignee of the present application and are hereby incorporated herein by reference, are primarily determined by the speed with which the processor fetches, interprets and executes instructions. In a system in which the operation of the processor is controlled by a control store which stores numerous microprogrammed addressable instructions with which the processor fetches, interprets and executes general instructions received from external devices; the speed with which these programmed addressable instructions are interpreted and executed by the various parts of the processor is an important factor in determining the performance characteristics of the machine.
Typically, to obtain the fastest speed possible, these instructions are directly executed; that is, the information contained in each instruction is coupled throughout the processor so that affected portions of the processor can directly execute the instruction in the least amount of time. This method of execution of the instructions is obviously very expensive in terms of the space required to couple the various bits of information contained in the instruction throughout the processor and also in terms of the logic circuitry used throughout the processor to interpret the instruction and control the processor accordingly. As the processor becomes more complicated the size of the programmed instructions will increase significantly, increasing the cost of the control store which stores these instructions, the amount of space consumed by additional conductors required to transfer the instruction throughout the processor and the amount of logic circuitry needed to interpret and execute the instruction.
Other processors which sacrifice performance for cost will utilize highly encoded instructions which will reduce the size or length of the instruction. This, of course, eliminates some of the conductors required to transfer the instruction throughout the processor and may reduce the amount of logic circuitry disposed throughout the processor for interpreting and executing the processor instructions. However, the performance characteristics of a processor utilizing this technique must suffer because of the extra time required for the additional decoding of each instruction.